Combinational Circuits

Overview

A combinational circuit has outputs that depend only on current inputs — no memory, no feedback. Given the same inputs, you always get the same outputs instantly (ignoring propagation delay).

Design flow: specification → truth table → Boolean expression → simplification → gate implementation.

Comparators

1-bit equality

F = A XNOR B = (A ⊕ B)′

n-bit magnitude comparator

Compare two n-bit numbers A and B, producing three outputs:

For cascaded ICs (e.g., 74HC85): each stage receives G_in, E_in, L_in from the lower stage and passes updated signals upward.

Encoders

An encoder converts 2ⁿ input lines (one active at a time) to an n-bit binary code.

4-to-2 Priority Encoder

Handles multiple simultaneous inputs; higher-indexed input has priority.

V = valid output (1 if any input is active).

Equations: A1 = I3 + I2; A0 = I3 + I2′·I1; V = I3 + I2 + I1 + I0

Decoders

A decoder converts an n-bit binary code to one of 2ⁿ output lines (one active at a time). The inverse of an encoder.

2-to-4 Decoder

Equations: Y0 = EN·A1′·A0′; Y1 = EN·A1′·A0; Y2 = EN·A1·A0′; Y3 = EN·A1·A0

A decoder can implement any Boolean function: connect the minterms you need to an OR gate. A 3-to-8 decoder + OR gate = any 3-variable SOP.

Multiplexers (MUX)

A multiplexer selects one of 2ⁿ data inputs and routes it to the output, controlled by n select lines.

4-to-1 MUX

Y = S1′·S0′·I0 + S1′·S0·I1 + S1·S0′·I2 + S1·S0·I3

MUX as function generator: set select lines as variables, connect constants (0/1) or expressions to data inputs to implement any Boolean function.

Demultiplexers (DEMUX)

Routes one input to one of 2ⁿ outputs. A decoder with a data input connected to EN is a DEMUX.

Code Converters

BCD to Excess-3

Add 3 (0011) to each BCD digit. Used historically for 9's-complement arithmetic.

BCD to 7-Segment

Seven output lines (a–g) drive display segments. Commonly implemented with ROM or combinational logic.

 _
|_|   segments: a (top), b (top-right), c (bottom-right),
|_|             d (bottom), e (bottom-left), f (top-left), g (middle)

Parity Generator/Checker

Parity bit added so the total number of 1s is even (even parity) or odd (odd parity).

• Even parity bit P = b₃ ⊕ b₂ ⊕ b₁ ⊕ b₀
• Checker: P ⊕ b₃ ⊕ b₂ ⊕ b₁ ⊕ b₀ = 0 (no error), 1 (single-bit error detected)

Detects odd numbers of bit errors; cannot correct or detect even numbers.

Timing Hazards

Static Hazard

A brief unwanted glitch at the output during input transitions, even though the final output should remain constant.

Cause: SOP/POS covering does not include a term bridging adjacent groups. Fix: Add a consensus term that overlaps the two groups involved in the transition.

Dynamic Hazard

Output changes 3+ times when it should change only once. Occurs in multi-level circuits. Fixed by restructuring to two-level logic.

Propagation Delay and Critical Path

Critical path delay = sum of gate delays along the longest input-to-output path
Maximum clock frequency f_max = 1 / t_critical_path

Minimize critical path by: - Reducing logic levels (two-level preferred for speed) - Using carry-lookahead instead of ripple-carry - Pipelining (adds latency but increases throughput)