Digital Circuits Cheatsheet

Logic Gates

Use this Digital Circuits reference while you build software engineering projects, review code, or refresh the syntax you reach for most.

Overview

Logic gates are the physical building blocks of digital circuits. Each gate implements a Boolean function, which is why the topic matters when you move from learning Python, JavaScript, Java, or C++ into computer architecture and systems courses. Gates are built from transistors (MOSFETs in modern CMOS technology) and are combined to realize any logic function.

Basic Gate Truth Tables

NOT (Inverter)

A	A′
0	1
1	0

AND

A	B	A · B
0	0	0
0	1	0
1	0	0
1	1	1

OR

A	B	A + B
0	0	0
0	1	1
1	0	1
1	1	1

NAND

A	B	(A · B)′
0	0	1
0	1	1
1	0	1
1	1	0

NOR

A	B	(A + B)′
0	0	1
0	1	0
1	0	0
1	1	0

XOR (Exclusive OR)

A	B	A ⊕ B
0	0	0
0	1	1
1	0	1
1	1	0

XNOR (Exclusive NOR)

A	B	(A ⊕ B)′
0	0	1
0	1	0
1	0	0
1	1	1

Gate Summary Table

Gate	Symbol	Output	CMOS transistors (2-input)
NOT	○—	HIGH when input LOW	1p + 1n
AND	D shape	HIGH only if all HIGH	4 (NAND + NOT)
OR	Curved	HIGH if any HIGH	4 (NOR + NOT)
NAND	D + bubble	LOW only if all HIGH	2p + 2n
NOR	Curved + bubble	HIGH only if all LOW	2p + 2n
XOR	Curved + extra arc	HIGH if odd number HIGH	~8–12
XNOR	XOR + bubble	HIGH if even number HIGH	~8–12

NAND and NOR are universal gates — any Boolean function can be built using only NANDs or only NORs.

Universal Gate Implementations

NOT from NAND

A ──┬── NAND ──── A′
    └──

Connect both NAND inputs together: (A · A)′ = A′

AND from NAND

A ──┐
    NAND ──── NAND ──── A · B
B ──┘    (self)

OR from NAND (De Morgan)

A ──── NAND ──┐
              NAND ──── A + B
B ──── NAND ──┘

OR from NOR (similar pattern)

A ──┐
    NOR ──── NOR ──── A + B
B ──┘    (self)

Multi-Input Gates

AND and OR gates extend naturally. XOR on >2 inputs uses cascade:

3-input XOR: (A ⊕ B) ⊕ C

Parity: n-input XOR outputs 1 when an odd number of inputs are 1.

Gate Timing Characteristics

Parameter	Meaning
Propagation delay (tₚ)	Time from input change to output reaching 50% of final value
tₚHL	High-to-Low output transition delay
tₚLH	Low-to-High output transition delay
tₚ (average)	(tₚHL + tₚLH) / 2
Rise/fall time	Time for output to move 10%→90% or 90%→10%
Critical path	Longest delay path through a circuit; limits clock speed

Fan-In and Fan-Out

Term	Definition
Fan-in	Number of inputs a gate can accept
Fan-out	Number of gate inputs a single output can drive without degradation
Typical CMOS fan-out	10–20 standard loads

Exceeding fan-out increases delay and may cause logic errors.

Logic Families (Historical + Modern)

Family	Full name	V_CC	Speed	Power
TTL	Transistor–Transistor Logic	5 V	Moderate	Moderate
CMOS	Complementary MOS	1.8–5 V	Fast	Very low (static)
ECL	Emitter-Coupled Logic	−5.2 V	Very fast	High
BiCMOS	Bipolar + CMOS	3.3–5 V	Fast	Low–moderate

Modern digital design uses CMOS almost exclusively; logic levels: - LOW: 0 – 0.8 V (TTL), 0 – 0.3×V_DD (CMOS) - HIGH: 2.0 – 5 V (TTL), 0.7×V_DD – V_DD (CMOS)

Wired Logic

In open-collector/open-drain outputs, connecting outputs together creates wired AND (pull-up resistor to V_CC):

Out_A ──┐
         ├──── Wired-AND output
Out_B ──┘

Used in I²C bus and interrupt lines.

Bubble Pushing (Gate Conversion)

Move bubbles (inversions) through a gate, swapping AND↔OR, to simplify schematics or match available parts:

Original	Equivalent (bubbles pushed)
NAND(A, B)	OR(A′, B′)
NOR(A, B)	AND(A′, B′)
AND(A, B)	NAND(A, B) + bubble on output

Rule: Adding/removing two bubbles on the same line cancels out (double negation).