Registers and Counters

Overview

Registers are groups of flip-flops that store multi-bit values. Counters are registers whose stored value increments (or decrements) in a defined sequence. Both are fundamental sequential building blocks.

Registers

Basic n-bit Register

n D flip-flops sharing a common clock. All bits are loaded simultaneously on the active clock edge.

D₃ D₂ D₁ D₀
|   |   |   |
FF  FF  FF  FF  (all share CLK)
|   |   |   |
Q₃ Q₂ Q₁ Q₀

Load enable: AND each Dᵢ with LOAD; OR with Qᵢ·LOAD′ to hold when LOAD=0.

Register with Synchronous Reset

D_eff = D·LOAD·RESET′ + Q·LOAD′·RESET′
      (Q=0 forced when RESET=1)

Register File

Array of registers with read/write ports, addressed by register number. Core of a CPU register file.

Shift Registers

A chain of D flip-flops where each FF's output feeds the next FF's input.

Serial-In Serial-Out (SISO)

D_in ──► FF₀ ──► FF₁ ──► FF₂ ──► FF₃ ──► D_out
              CLK (all FFs share)

Data shifts one position right on each clock. n-bit shift register has n-cycle delay.

Serial-In Parallel-Out (SIPO)

Same chain; tap Q₀–Qₙ₋₁ simultaneously. Use: serial-to-parallel conversion (SPI, UART receiver).

Parallel-In Serial-Out (PISO)

Load n bits at once (synchronous parallel load), then shift out serially. Use: parallel-to-serial conversion (UART transmitter).

Parallel-In Parallel-Out (PIPO)

Standard register; load and read all bits in one clock.

Universal Shift Register (74HC194)

Shift Register Applications

Linear Feedback Shift Register (LFSR)

XOR of selected tap outputs fed back to input. Produces a maximal-length pseudo-random sequence (2ⁿ−1 states for n-bit LFSR).

4-bit LFSR (taps at positions 4, 3):
[Q₄]─[Q₃]─[Q₂]─[Q₁]─►
  └────XOR──────────────┘

Uses: CRC generation, test pattern generation, encryption keystream.

Counters Overview

Asynchronous (Ripple) Counter

T flip-flops in series; each FF's Q feeds the next FF's CLK.

CLK ──► FF₀ (LSB) ──Q₀──► FF₁ ──Q₁──► FF₂ ──Q₂──► FF₃ (MSB)

• Each stage divides the clock by 2.
• Propagation ripple delay accumulates: tₚ_total = n × t_FF.
• NOT suitable for high-speed synchronous systems — different bits settle at different times (glitches in combinational logic using these outputs).

3-bit Ripple Counter Sequence

Synchronous Binary Counter

All FFs share a single CLK. Logic determines each FF's T input.

T flip-flop equations (n-bit up counter): - T₀ = 1 (always toggles) - T₁ = Q₀ - T₂ = Q₁ · Q₀ - T₃ = Q₂ · Q₁ · Q₀ - Tᵢ = Q_{i-1} · Q_{i-2} · … · Q₀ (carry enable)

A carry enable chain allows cascading: ENₚ and ENₜ in the 74HC163.

74HC163 — 4-bit Synchronous Counter

Priority: CLR̄ > LOAD̄ > Count > Hold

Modulo-M Counter

Count from 0 to M−1, then reset. Choose smallest n where 2ⁿ ≥ M.

Method (synchronous clear, e.g. 74HC163): A synchronous CLR takes effect on the next clock edge, so detect the last state to keep, M−1 — the counter then clears instead of advancing to M. (Detecting M would let state M live for a full cycle → a mod-(M+1) counter.)

Example: Mod-6 counter (M=6, n=3) Detect state 5 (101₂): CLR̄ = (Q₂·Q₀)′.

Sequence: 0→1→2→3→4→5→0 — state 5 lasts one full clock period; the edge that would have produced 6 clears instead.

Method (asynchronous clear, e.g. 74HC161): Detect state M itself (mod-6: Q₂·Q₁ for 110₂) and assert the async CLR. State M appears only as a nanoseconds-wide glitch — simpler decode, but the glitch can clock or confuse downstream logic; prefer the synchronous method.

Gray Code Counter

Adjacent states differ by one bit; eliminates glitches when sampling count with combinational logic.

Binary to Gray: Gᵢ = Bᵢ ⊕ Bᵢ₊₁ (G_MSB = B_MSB)

Ring and Johnson Counters

Ring Counter (n-bit, one-hot)

One 1 circulates through n FFs. Always has exactly one FF = 1. States: n (one per FF). Needs initialization (preset one FF to 1).

Johnson (Switch-Tail) Counter

Q̄_last fed to D_first. States: 2n (double a ring counter's states).

4-bit Johnson sequence: