Computer Architecture Cheatsheet

Data Representation

Use this Computer Architecture reference while you build software engineering projects, review code, or refresh the syntax you reach for most.

Number Bases

Binary, octal, and hex recur throughout systems work — memory addresses, bit masks, permissions, network packets.

Base	Name	Digits	Prefix
2	Binary	0–1	`0b`
8	Octal	0–7	`0o`
10	Decimal	0–9	—
16	Hexadecimal	0–9, A–F	`0x`

Conversion — decimal → binary (repeated division by 2):

45 ÷ 2 = 22 R 1   ← LSB
22 ÷ 2 = 11 R 0
11 ÷ 2 =  5 R 1
 5 ÷ 2 =  2 R 1
 2 ÷ 2 =  1 R 0
 1 ÷ 2 =  0 R 1   ← MSB
45₁₀ = 0b101101

Hex ↔ binary: each hex digit = 4 bits exactly.

0xAB = 1010 1011
0x3F = 0011 1111

Integer Encodings

Unsigned

Range for n bits: 0 to 2ⁿ − 1

Value = Σ bᵢ · 2ⁱ (i from 0 to n−1)

Sign-Magnitude

MSB = sign bit (0 = +, 1 = −)
Has +0 and −0 (two zeros)
Range: −(2ⁿ⁻¹ − 1) to +(2ⁿ⁻¹ − 1)
Rarely used in modern CPUs (awkward arithmetic)

One's Complement

Negate by flipping all bits
Still has +0 and −0
Range: −(2ⁿ⁻¹ − 1) to +(2ⁿ⁻¹ − 1)

Two's Complement (universal modern standard)

Negate: flip all bits, add 1
Only one zero
Range: −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1
MSB has weight −2ⁿ⁻¹

n-bit	Min	Max
8	−128	127
16	−32,768	32,767
32	−2,147,483,648	2,147,483,647
64	−9.22 × 10¹⁸	9.22 × 10¹⁸

Example (8-bit):

Bits	Unsigned	Two's Complement
`0000 0000`	0	0
`0111 1111`	127	127
`1000 0000`	128	−128
`1111 1111`	255	−1

Overflow: occurs when the result exceeds the representable range. Detected by: carry into MSB ≠ carry out of MSB.

Bitwise Operations

Operation	Symbol	Example (8-bit)
AND	`&`	`1010 & 1100 = 1000`
OR	`\|`	`1010 \| 1100 = 1110`
XOR	`^`	`1010 ^ 1100 = 0110`
NOT	`~`	`~1010 = 0101`
Left shift	`<<`	`0001 << 2 = 0100` (×4)
Right shift (logical)	`>>`	`1000 >> 2 = 0010`
Right shift (arithmetic)	`>>`	`1000 >> 2 = 1110` (sign-extends)

Shifts multiply/divide by powers of 2. Arithmetic right shift preserves the sign bit.

IEEE 754 Floating-Point

Formats

Format	Total bits	Sign	Exponent	Mantissa	Approx. decimal digits
Half (FP16)	16	1	5	10	~3
Single (float)	32	1	8	23	~7
Double (double)	64	1	11	52	~15–16
Extended (x87)	80	1	15	63+1	~18–19

Layout (32-bit single)

Bit 31   30–23        22–0
  S    EEEEEEEE   MMMMMMMMMMMMMMMMMMMMMMM
sign   exponent     mantissa (fraction)

Value formula (normalized): (−1)ˢ × 1.M × 2^(E − bias)

Bias = 127 for single, 1023 for double

Special Values

Exponent	Mantissa	Value
All 0s	All 0s	±0
All 0s	Non-zero	Subnormal (denormal)
All 1s	All 0s	±∞
All 1s	Non-zero	NaN (quiet or signaling)
Other	Any	Normalized number

Example: 0.1 in single precision

0.1 cannot be represented exactly — nearest value ≈ 0.100000001490116. This is why 0.1 + 0.2 ≠ 0.3 in most languages.

Rounding Modes (IEEE 754)

Mode	Description
Round to nearest even	Default; ties go to even LSB
Round toward +∞	Ceiling
Round toward −∞	Floor
Round toward 0	Truncation

Character Encodings

Standard	Bits	Notes
ASCII	7	128 characters; 0–31 control, 32–127 printable
Latin-1 (ISO 8859-1)	8	Extends ASCII to 256 chars
UTF-8	8–32	Variable-width; ASCII-compatible; universal
UTF-16	16 or 32	Used internally by Windows, Java
UTF-32	32	Fixed-width; wastes space

UTF-8 encoding scheme:

Code point range	Byte 1	Byte 2	Byte 3	Byte 4
U+0000–U+007F	`0xxxxxxx`	—	—	—
U+0080–U+07FF	`110xxxxx`	`10xxxxxx`	—	—
U+0800–U+FFFF	`1110xxxx`	`10xxxxxx`	`10xxxxxx`	—
U+10000–U+10FFFF	`11110xxx`	`10xxxxxx`	`10xxxxxx`	`10xxxxxx`

Boolean / Logic Gates

Gate	Symbol	Truth table (A, B → Y)
AND	A · B	00→0, 01→0, 10→0, 11→1
OR	A + B	00→0, 01→1, 10→1, 11→1
NOT	Ā	0→1, 1→0
NAND	¬(A·B)	00→1, 01→1, 10→1, 11→0
NOR	¬(A+B)	00→1, 01→0, 10→0, 11→0
XOR	A ⊕ B	00→0, 01→1, 10→1, 11→0
XNOR	¬(A⊕B)	00→1, 01→0, 10→0, 11→1

NAND and NOR are each functionally complete — any Boolean function can be built from either alone.

Endianness

Name	Byte order	Used by
Big-endian	MSB at lowest address	Network protocols, SPARC, older MIPS
Little-endian	LSB at lowest address	x86, x86-64, ARM (LE mode), RISC-V
Bi-endian	Configurable	ARM, POWER, MIPS

Example — storing 0x12345678 at address 0x100:

Address	Big-endian	Little-endian
0x100	0x12	0x78
0x101	0x34	0x56
0x102	0x56	0x34
0x103	0x78	0x12

Data Alignment

A datum of size n bytes is naturally aligned when its address is a multiple of n.
Misaligned accesses may cause: hardware exceptions (strict architectures like SPARC), silent performance penalties (x86), or undefined behavior (C).
Structs are padded to satisfy alignment of their largest member.

struct Example {
    char  a;   // 1 byte at offset 0
    // 3 bytes padding
    int   b;   // 4 bytes at offset 4 (aligned to 4)
    char  c;   // 1 byte at offset 8
    // 3 bytes padding (to make sizeof = 12)
};