Computer Architecture Cheatsheet

Data Representation

Use this Computer Architecture reference while you build software engineering projects, review code for technical interview prep, or polish examples for a software engineer resume.

Number Bases

Binary, octal, and hex recur throughout systems work — memory addresses, bit masks, permissions, network packets.

BaseNameDigitsPrefix
2Binary0–10b
8Octal0–70o
10Decimal0–9
16Hexadecimal0–9, A–F0x

Conversion — decimal → binary (repeated division by 2):

45 ÷ 2 = 22 R 1   ← LSB
22 ÷ 2 = 11 R 0
11 ÷ 2 =  5 R 1
 5 ÷ 2 =  2 R 1
 2 ÷ 2 =  1 R 0
 1 ÷ 2 =  0 R 1   ← MSB
45₁₀ = 0b101101

Hex ↔ binary: each hex digit = 4 bits exactly.

0xAB = 1010 1011
0x3F = 0011 1111

Integer Encodings

Unsigned

Range for n bits: 0 to 2ⁿ − 1

Value = Σ bᵢ · 2ⁱ (i from 0 to n−1)

Sign-Magnitude

  • MSB = sign bit (0 = +, 1 = −)
  • Has +0 and −0 (two zeros)
  • Range: −(2ⁿ⁻¹ − 1) to +(2ⁿ⁻¹ − 1)
  • Rarely used in modern CPUs (awkward arithmetic)

One's Complement

  • Negate by flipping all bits
  • Still has +0 and −0
  • Range: −(2ⁿ⁻¹ − 1) to +(2ⁿ⁻¹ − 1)

Two's Complement (universal modern standard)

  • Negate: flip all bits, add 1
  • Only one zero
  • Range: −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1
  • MSB has weight −2ⁿ⁻¹
n-bitMinMax
8−128127
16−32,76832,767
32−2,147,483,6482,147,483,647
64−9.22 × 10¹⁸9.22 × 10¹⁸

Example (8-bit):

BitsUnsignedTwo's Complement
0000 000000
0111 1111127127
1000 0000128−128
1111 1111255−1

Overflow: occurs when the result exceeds the representable range. Detected by: carry into MSB ≠ carry out of MSB.

Bitwise Operations

OperationSymbolExample (8-bit)
AND&1010 & 1100 = 1000
OR|1010 | 1100 = 1110
XOR^1010 ^ 1100 = 0110
NOT~~1010 = 0101
Left shift<<0001 << 2 = 0100 (×4)
Right shift (logical)>>1000 >> 2 = 0010
Right shift (arithmetic)>>1000 >> 2 = 1110 (sign-extends)

Shifts multiply/divide by powers of 2. Arithmetic right shift preserves the sign bit.

IEEE 754 Floating-Point

Formats

FormatTotal bitsSignExponentMantissaApprox. decimal digits
Half (FP16)161510~3
Single (float)321823~7
Double (double)6411152~15–16
Extended (x87)8011563+1~18–19

Layout (32-bit single)

Bit 31   3023        220
  S    EEEEEEEE   MMMMMMMMMMMMMMMMMMMMMMM
sign   exponent     mantissa (fraction)

Value formula (normalized): (−1)ˢ × 1.M × 2^(E − bias)

  • Bias = 127 for single, 1023 for double

Special Values

ExponentMantissaValue
All 0sAll 0s±0
All 0sNon-zeroSubnormal (denormal)
All 1sAll 0s±∞
All 1sNon-zeroNaN (quiet or signaling)
OtherAnyNormalized number

Example: 0.1 in single precision

0.1 cannot be represented exactly — nearest value ≈ 0.100000001490116. This is why 0.1 + 0.2 ≠ 0.3 in most languages.

Rounding Modes (IEEE 754)

ModeDescription
Round to nearest evenDefault; ties go to even LSB
Round toward +∞Ceiling
Round toward −∞Floor
Round toward 0Truncation

Character Encodings

StandardBitsNotes
ASCII7128 characters; 0–31 control, 32–127 printable
Latin-1 (ISO 8859-1)8Extends ASCII to 256 chars
UTF-88–32Variable-width; ASCII-compatible; universal
UTF-1616 or 32Used internally by Windows, Java
UTF-3232Fixed-width; wastes space

UTF-8 encoding scheme:

Code point rangeByte 1Byte 2Byte 3Byte 4
U+0000–U+007F0xxxxxxx
U+0080–U+07FF110xxxxx10xxxxxx
U+0800–U+FFFF1110xxxx10xxxxxx10xxxxxx
U+10000–U+10FFFF11110xxx10xxxxxx10xxxxxx10xxxxxx

Boolean / Logic Gates

GateSymbolTruth table (A, B → Y)
ANDA · B00→0, 01→0, 10→0, 11→1
ORA + B00→0, 01→1, 10→1, 11→1
NOTĀ0→1, 1→0
NAND¬(A·B)00→1, 01→1, 10→1, 11→0
NOR¬(A+B)00→1, 01→0, 10→0, 11→0
XORA ⊕ B00→0, 01→1, 10→1, 11→0
XNOR¬(A⊕B)00→1, 01→0, 10→0, 11→1

NAND and NOR are each functionally complete — any Boolean function can be built from either alone.

Endianness

NameByte orderUsed by
Big-endianMSB at lowest addressNetwork protocols, SPARC, older MIPS
Little-endianLSB at lowest addressx86, x86-64, ARM (LE mode), RISC-V
Bi-endianConfigurableARM, POWER, MIPS

Example — storing 0x12345678 at address 0x100:

AddressBig-endianLittle-endian
0x1000x120x78
0x1010x340x56
0x1020x560x34
0x1030x780x12

Data Alignment

  • A datum of size n bytes is naturally aligned when its address is a multiple of n.
  • Misaligned accesses may cause: hardware exceptions (strict architectures like SPARC), silent performance penalties (x86), or undefined behavior (C).
  • Structs are padded to satisfy alignment of their largest member.
struct Example {
    char  a;   // 1 byte at offset 0
    // 3 bytes padding
    int   b;   // 4 bytes at offset 4 (aligned to 4)
    char  c;   // 1 byte at offset 8
    // 3 bytes padding (to make sizeof = 12)
};