Computer Architecture Cheatsheet
I/O and Buses
Use this Computer Architecture reference while you build software engineering projects, review code for technical interview prep, or polish examples for a software engineer resume.
I/O Fundamentals
I/O devices connect to the CPU and memory through buses — shared communication channels. The CPU communicates with devices via:
| Method | Description | Address space |
|---|---|---|
| Memory-mapped I/O (MMIO) | Device registers appear as memory addresses | Unified with RAM |
| Port-mapped I/O (PMIO) | Separate I/O address space; in/out instructions | x86-only, 64 K ports |
MMIO is universal; port I/O is an x86 legacy used mainly for ISA-compatible devices.
Bus Characteristics
| Property | Description |
|---|---|
| Width | Number of data lines (bits transferred in parallel) |
| Clock speed | Transfers per second (synchronous) or handshake-based (async) |
| Bandwidth | width × clock (peak) |
| Latency | Time from request to first byte |
| Shared vs point-to-point | Shared buses arbitrate; point-to-point are always dedicated |
Polling vs Interrupts vs DMA
Polling (Programmed I/O, PIO)
CPU repeatedly reads a device status register until ready, then reads/writes data.
while (!(device->status & READY)) // spin ; data = device->data_register;
- Pro: simple, predictable latency for fast devices
- Con: wastes CPU cycles (busy-wait)
Interrupts
Device signals CPU when ready. CPU saves state, runs Interrupt Service Routine (ISR), resumes.
| Step | Action |
|---|---|
| 1 | CPU issues I/O command to device |
| 2 | CPU continues executing other work |
| 3 | Device raises interrupt line (IRQ) |
| 4 | CPU acknowledges, saves PC + flags, masks IRQ |
| 5 | CPU jumps to ISR via interrupt vector table |
| 6 | ISR reads/writes data, clears interrupt |
| 7 | CPU restores state, resumes interrupted task |
Interrupt priority: hardware has priority levels; higher-priority IRQs preempt lower. x86 has 256 interrupt vectors (0–255); vectors 0–31 are CPU exceptions, 32–255 are maskable hardware interrupts.
DMA (Direct Memory Access)
DMA controller moves data between device and memory without CPU per-byte involvement.
CPU DMA Controller Device │ │ │ │──start transfer──►│ │ │ │ (src, dst, count)│ │ │ │ │──request data──────────►│ │ (CPU free) │◄─── data ──────────────│ │ │──write to memory │ │ │ (repeats count times) │ │ │──interrupt CPU──────────►│ │◄──done interrupt──│ │
- CPU overhead: just setup + completion interrupt (not per-byte)
- Required for fast devices (NICs, NVMe, GPUs)
- Modern: IOMMU (Input-Output MMU) virtualizes DMA addresses for safety
Bus Standards and Interconnects
Historical Internal Buses
| Bus | Width | Speed | Era |
|---|---|---|---|
| ISA | 16-bit | 8 MHz | 1984–1990s |
| PCI | 32/64-bit | 33/66 MHz | 1992–2004 |
| AGP | 32-bit | 66 MHz × 1/2/4/8 | 1997–2004 |
| PCI-X | 64-bit | 133 MHz | Servers |
PCIe (PCI Express) — Current Standard
Point-to-point serial lanes; each lane = 1 differential pair each way.
| Version | Per-lane bandwidth | x16 bandwidth | Year |
|---|---|---|---|
| PCIe 3.0 | 1 GB/s each direction | 16 GB/s | 2010 |
| PCIe 4.0 | 2 GB/s | 32 GB/s | 2017 |
| PCIe 5.0 | 4 GB/s | 64 GB/s | 2019 |
| PCIe 6.0 | 8 GB/s | 128 GB/s | 2022 |
Common configurations: x1, x4, x8, x16. GPU slots: x16. NVMe SSD: x4.
Storage Interfaces
| Interface | Max bandwidth | Protocol | Notes |
|---|---|---|---|
| SATA III | 600 MB/s | AHCI | Legacy HDDs/SSDs; shared bus |
| M.2 NVMe (PCIe 3.0 x4) | 3.5 GB/s | NVMe | Modern SSD |
| M.2 NVMe (PCIe 4.0 x4) | 7 GB/s | NVMe | Fast consumer SSD |
| M.2 NVMe (PCIe 5.0 x4) | 14 GB/s | NVMe | Cutting-edge |
| U.2 / U.3 | PCIe x4 | NVMe | Enterprise SSD |
External / Peripheral
| Interface | Max speed | Notes |
|---|---|---|
| USB 2.0 | 480 Mb/s | Keyboard, mouse |
| USB 3.2 Gen 1 | 5 Gb/s | Flash drives |
| USB 3.2 Gen 2 | 10 Gb/s | External SSDs |
| USB 3.2 Gen 2×2 | 20 Gb/s | Dual lane |
| USB4 Gen 3×2 / Thunderbolt 4 | 40 Gb/s | USB-C; tunnels PCIe + DP |
| Thunderbolt 5 | 120 Gb/s | Bidirectional burst |
| Ethernet | 1–400 Gb/s | LAN/WAN |
| DisplayPort 2.1 | 80 Gb/s | Video |
| HDMI 2.1 | 48 Gb/s | Video + audio |
CPU Interconnects (Multi-Socket)
| Technology | Vendor | Bandwidth | Notes |
|---|---|---|---|
| UPI (Ultra Path Interconnect) | Intel | 10.4–20 GT/s | 2-socket Xeon |
| Infinity Fabric | AMD | Variable | EPYC CCD-to-CCD + I/O die |
| NVLink 4 | NVIDIA | 900 GB/s total | GPU-to-GPU |
| CXL (Compute Express Link) | Industry | PCIe-based | Memory/device coherency |
Interrupt Controllers
| Component | Description |
|---|---|
| PIC (8259A) | Legacy; 8 IRQ lines, cascade for 16; x86 original |
| APIC (Advanced PIC) | Per-core Local APIC + I/O APIC; up to 255 IRQs; modern x86 |
| MSI / MSI-X | Message Signaled Interrupts — device writes to memory-mapped register; no IRQ wire; PCIe default |
| GIC (ARM) | Generic Interrupt Controller; Cortex-A systems |
MSI-X supports up to 2048 interrupt vectors per device, enabling per-queue interrupts in NICs and NVMe controllers (no lock contention).
Bus Arbitration
For shared buses, the bus master must be decided:
| Method | Description |
|---|---|
| Daisy chain | Priority by position on chain; fast but unfair |
| Centralized | Bus arbiter decides; fair (round-robin) |
| Distributed | Each device signals on dedicated lines; priority encoded |
| Token passing | Only device holding token can use bus |
Modern systems use point-to-point links (PCIe, Infinity Fabric) that eliminate arbitration — each link is dedicated.
I/O Performance Metrics
| Metric | Definition |
|---|---|
| Throughput | MB/s or GB/s sustained |
| IOPS | I/O operations per second (random small I/O) |
| Latency | Time from command issue to data received |
| Queue depth | Number of in-flight I/O requests |
IOPS vs throughput trade-off: small random reads maximize IOPS; large sequential reads maximize throughput.
Example: NVMe SSD — 1 M IOPS @ 4 KB random; 7 GB/s sequential throughput.