Computer Architecture Cheatsheet

Performance

Use this Computer Architecture reference while you build software engineering projects, review code, or refresh the syntax you reach for most.

The Iron Law of Performance

CPU Time = Instruction Count × CPI × Clock Cycle Time

Or equivalently:

CPU Time = (Instruction Count × CPI) / Clock Rate

Variable	Symbol	Determined by
Instruction count	IC	Algorithm, compiler, ISA
Cycles per instruction	CPI	Microarchitecture (pipeline, OOO, caches)
Clock cycle time	T = 1/f	Implementation (process node, circuit design)

These three variables trade off. RISC reduces CPI but may increase IC vs CISC; deeper pipelines increase f but raise branch penalty (CPI).

CPI Breakdown

Effective CPI = Base CPI + Memory stall CPI + Branch stall CPI + ...

Source	CPI contribution formula
Load-use stalls	freq_load_use × 1 cycle
Branch mispredictions	freq_branch × miss_rate × penalty
L1 data misses	mem_accesses_per_instr × L1_miss_rate × L2_hit_time
L2 misses	mem_accesses_per_instr × L2_miss_rate × memory_time

Example: - Base CPI = 1.0 - Branch freq = 15%, miss rate = 8%, penalty = 14 cycles → +0.168 - Load freq = 30%, L1 miss rate = 4%, L2 hit = 10 cycles → +0.12 - L2 miss rate = 1%, memory = 200 cycles → +0.06 - Effective CPI = 1 + 0.168 + 0.12 + 0.06 = 1.348

Speedup

Speedup = Old time / New time = 1 / ((1 − f) + f/s)

Where f = fraction of execution improved, s = speedup of that fraction.

This is Amdahl's Law in execution-time form.

Example: If 70% of time is in a routine sped up 10×:

Speedup = 1 / (0.30 + 0.70/10) = 1 / (0.30 + 0.07) = 1 / 0.37 ≈ 2.70×

Even though the routine is 10× faster, overall speedup is only 2.70×.

Benchmarks

SPEC CPU Benchmarks

Suite	Focus	Example workloads
SPECint (CINT2017)	Integer performance	GCC, Perl, x264, mcf
SPECfp (CFP2017)	Floating-point	BLAS, weather sim, fluid dynamics
SPECrate	Throughput (multi-core)	Run N copies simultaneously
SPECspeed	Latency (single thread)	One copy, minimize time

SPEC ratio = reference time / measured time. Geometric mean across all benchmarks.

Other Common Benchmarks

Benchmark	Measures
LINPACK / HPL	Peak FP throughput (Top500 HPC ranking)
STREAM	Memory bandwidth (4 kernels: copy, scale, add, triad)
LMbench	Detailed latency/bandwidth (memory, syscall)
Dhrystone	Integer/compiler throughput (old; not representative)
Geekbench	Consumer single/multi-core (opaque; use with skepticism)
MLPerf	ML training and inference throughput
PARSEC	Parallel workloads (shared-memory multicore)

Benchmark pitfalls: peak performance ≠ sustained; microbenchmarks may not predict real workload performance; compiler flags and libraries dramatically affect results.

Memory Performance Metrics

Metric	Formula	Typical values
AMAT	Hit time + Miss rate × Miss penalty	1–10 cycles typical
Bandwidth	Width × frequency	50–100+ GB/s (DDR5 dual-channel)
Memory-level parallelism (MLP)	Avg. concurrent outstanding misses	8–16 for out-of-order CPUs

STREAM Benchmark Kernel Bandwidths (indicative)

Kernel	Operations
Copy	a[i] = b[i]
Scale	a[i] = k × b[i]
Add	a[i] = b[i] + c[i]
Triad	a[i] = b[i] + k × c[i] (main kernel)

Roofline Model

The Roofline model identifies whether a kernel is compute-bound or memory-bandwidth-bound.

Performance      │           ╱ Roofline
(GFLOPS/s)       │          ╱
                 │  Memory ╱  ─────────── Peak compute
                 │  bound ╱  Compute
                 │       ╱   bound
                 └──────────────────────────
                       Arithmetic Intensity
                       (FLOPS / byte)

Arithmetic Intensity (AI) = FLOPS / bytes transferred from DRAM

Ridge point = Peak compute / Peak bandwidth

Regime	Condition	Bottleneck	Fix
Memory-bound	AI < Ridge point	DRAM bandwidth	Better cache use, prefetch, compression
Compute-bound	AI > Ridge point	ALU throughput	Vectorize, fuse ops, reduce precision

Example (H100): Peak FP32 = 67 TFLOPS, Memory BW = 3.35 TB/s → Ridge point = 67,000 / 3,350 ≈ 20 FLOP/byte

Dense matrix multiply (GEMM) has AI ≈ N/2 (for N×N matrix) → compute-bound for any reasonable N.

Measuring Performance

Tool (Linux)	What it measures
`perf stat`	Hardware PMU: cycles, instructions, cache misses, branch mispredictions
`perf record/report`	Call-graph profiling with hardware counters
`valgrind --tool=cachegrind`	Simulated cache miss rates
`vtune` (Intel)	Detailed microarchitecture analysis
`gprof`	Sampling profiler (software, low overhead)
`time`	Wall time, user time, system time
`sar`, `iostat`	System-wide CPU, I/O utilization

Key PMU Events (x86)

Event	Counter name
Clock cycles	`cpu-cycles`
Instructions retired	`instructions`
L1D misses	`L1-dcache-load-misses`
LLC misses	`LLC-load-misses`
Branch mispredictions	`branch-misses`
dTLB misses	`dTLB-load-misses`

IPC from perf:

perf stat -e cycles,instructions ./program
# instructions / cycles = IPC

Power-Performance Trade-offs

Metric	Formula	Notes
Energy	E = P × time	Joules
Energy-delay product (EDP)	EDP = E × time = P × time²	Balances energy and speed equally
Energy-delay² product (ED²P)	ED²P = E × time² = P × time³	Weights delay more heavily — favors performance
Performance per watt	GFLOPS/W or IPS/W	Mobile / HPC efficiency metric

Dennard Scaling (ended ~2005): as transistors shrink, voltage drops → power stays constant at same performance. Breakdown: leakage current no longer shrinks proportionally → power density rises → "power wall."

The Power Wall: CPUs can no longer increase clock speed without unacceptable power/thermal cost. Response: more cores at lower frequency.

Performance Summary Table

Technique	Reduces	Affects
Better algorithm	Instruction count	IC ↓
Better compiler	IC, CPI	IC ↓, CPI ↓
Bigger caches	Cache miss stalls	CPI ↓
Out-of-order execution	ILP stalls	CPI ↓
Branch prediction	Control stalls	CPI ↓
Higher clock rate	Cycle time	T ↓ (but CPI may ↑ with deeper pipe)
SIMD / vectorization	Instruction count	IC ↓ (same work, fewer instructions)
More cores (parallel code)	Wall-clock time	Time ↓ (IC × CPI × T unchanged per thread)
DVFS / power gating	Power	E ↓ (some T ↑ trade-off)