Computer Architecture Cheatsheet

Overview

Use this Computer Architecture reference while you build software engineering projects, review code for technical interview prep, or polish examples for a software engineer resume.

What Computer Architecture Studies

Computer architecture defines the abstract interface between software and hardware — what a programmer (or compiler) can assume the machine will do. It spans three interrelated levels:

Level	Name	Concerns
ISA	Instruction Set Architecture	Instructions, registers, addressing modes, data types
Microarchitecture	Implementation	Pipeline stages, cache sizes, execution units
Digital logic	Circuits	Gates, flip-flops, ALUs, memory cells

ISA is the contract. Two CPUs with the same ISA (e.g., x86-64) can run identical binaries even if their microarchitectures differ completely (e.g., Intel Raptor Lake vs AMD Zen 4).

Key Abstractions

Von Neumann model — single shared memory holds both instructions and data; CPU fetches, decodes, and executes one instruction at a time (conceptually). Almost every general-purpose CPU follows this.
Harvard architecture — separate instruction and data memories. Common in microcontrollers (AVR, PIC) and DSPs; also used internally by modern CPUs via split I-cache / D-cache.
Stored-program concept — programs are data; they can be loaded, moved, and even self-modified at run time.

The Classic Von Neumann Machine

+------------------+         +-------------------+
|      Memory      |<------->|        CPU        |
| (instructions +  |  bus    | +------+ +------+ |
|      data)       |         | | ALU  | |Regs  | |
+------------------+         | +------+ +------+ |
         ^                   |    Control Unit    |
         |                   +-------------------+
         v
    I/O Devices

Components:

Component	Role
ALU	Arithmetic & logic operations
Registers	Fast, on-chip storage (words)
Control Unit	Fetch-decode-execute sequencing
Memory	Addressable byte/word storage
I/O	Peripherals, buses, DMA

Instruction Execution Cycle

Fetch — load instruction from memory[PC] into IR
Decode — control unit interprets opcode and operand fields
Execute — ALU or memory operation performed
Write-back — result stored to register or memory
PC update — PC ← PC + instruction_length (or branch target)

Design Goals and Trade-offs

Goal	Tension
High performance	More power, more area, more complexity
Low power	Slower clocks, fewer execution units
Low cost	Fewer transistors, simpler design
Compatibility	Constraints on ISA evolution
Security	Side-channel vulnerabilities (Spectre, Meltdown)

Major ISA Families

Family	Style	Examples	Notes
x86 / x86-64	CISC	Intel Core, AMD Ryzen	Dominant desktop/server
ARM (A-profile)	RISC	Apple M-series, Cortex-A	Dominant mobile/embedded
RISC-V	RISC (open)	SiFive, VexRiscv	Growing in research & embedded
MIPS	RISC	Classic textbook ISA	Largely retired from mainstream
POWER	RISC	IBM POWER10	High-end servers

Flynn's Taxonomy of Parallelism

Class	Instruction streams	Data streams	Example
SISD	1	1	Classic uniprocessor
SIMD	1	Multiple	AVX/SSE vector units, GPUs
MISD	Multiple	1	Rare; fault-tolerant pipelines
MIMD	Multiple	Multiple	Multi-core CPUs, clusters

Measures of Complexity

Transistor count — billions on modern dies (Apple M3 Ultra: ~184 B)
Die area — mm²; area = cost driver
TDP — Thermal Design Power (Watts), sustained power envelope
Process node — TSMC 3 nm, Intel 7, etc. (marketing labels, not literal dimensions)